With scaling to the nanometer regime and improvements in trans-conductance and parasitics, many sophisticated integrated systems can now be implemented in CMOS. However, as feature sizes shrink, new challenges arise, as process, voltage, and temperature (PVT) variations grow larger and more difficult to control. For instance, the small number of dopants in the channel becomes an important source of randomness, rendering traditional techniques (e.g., common-centroid or interdigitated designs) ineffective. From an RF system perspective, such variations can be detrimental since parameters such as gain are not well controlled.
There is a need for a device structure and method of operation for sophisticated integrated systems which increases device fabrication and manufacturing yield and which adapts such devices to changing environmental factors present in operational use.